View R2A20124ASP-W0_3491274.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r03ds0031ej0300 rev.3.00 page 1 of 12 mar 11, 2011 preliminary datasheet r2a20124afp/r2a20124asp synchronous phase shift full-bridge control ic series description the r2a20124afp/r2a20124asp controls a full-bridge phase shift circuit and secondary synchronous rectification. the r2a20124afp/r2a20124asp has adjustable delay time functions which make zvs of primary side and make loss of body diode of primary switching device minimal. the r2a20124afp/r2a20124asp is based on ha16163/r2a2 0121. and ramp slope compensation circuit is built- in as an additional function. also its output driver circuits are improved to enlarge gate drive output voltage swing from vref to vcc. in addition r2a20124afp has on/off function of synchronous rectification and includes amplifier which detect input current signal. features ? maximum ratings ? supply voltage vcc: 20 v ? operating junction temperature tj-opr: ?40 to +125c ? electrical characteristics ? vfb feedback voltage vfb(?): 1.25 v ? 2.0% ? uvlo (under voltage lockout) op eration start voltage vh: 8.4 v ? 0.7 v ? uvlo operation shutdown voltage vl: 8.0 v ? 0.6 v ? uvlo hysteresis voltage dvuvl: 0.4 v ? 0.1 v ? output voltage swing of out-a, b, c, d, and e for gate drive: gnd to vcc ? functions r2a20124afp/r2a20124asp ? full-bridge phase-shift switching circuit with adjustable delay times ? pulse by pulse current limit ? synchronization i/o for the oscillator ? ramp sloping adjustor ? error amplifier built-in ? soft start function r2a20124afp ? synchronous rectification on/off control ? remote on/off control ? amplified output of current sense input voltage: cs ? package lineup ? pb-free lqfp-40: r2a20124afp ? pb-free sop-20: r2a20124asp ordering information part no. package name package code taping spec. r2a20124afp-w0 2000 pcs./one taping product r2a20124afp-w5 2000 pcs./one taping product r2a20124afp-u0 ? r2a20124afp-u5 fp-40ev plqp0040jb-c ? R2A20124ASP-W0 2000 pcs./one taping product r2a20124asp-w5 2000 pcs./one taping product r2a20124asp-u0 ? r2a20124asp-u5 fp-20dav prsp0020dd-b ? r03ds0031ej0300 rev.3.00 mar 11, 2011
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 2 of 12 mar 11, 2011 modified points from r2a20121sp ? the swing level of the maximum output voltage is changed from vref to vcc. ? ramp sloping compensation circuit is added. ? synchronous rectification control is possible to turned off at light load. (only r2a20124afp) ? on/off control terminal for remote is added. (only r2a20124afp) illustrative circuit r2a20124afp/asp note: ? 1. only r2a20124afp vcc out -a out -c cs ramp fb(?) vref rt sync ss cs- out( ? 1 ) sec-cont( ? 1 ) sgnd out -b out -f out -e out -d delay -3 delay -2 delay -1 comp vin dc 12 v vbias (dc 12 v) dc 12 v dc 12 v dc 12 v dc 12 v ramp -slp remote( ? 1 ) pgnd
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 3 of 12 mar 11, 2011 pin arrangement cs ramp ss comp fb(?) cs-out n.c. n.c. n.c. n.c. delay-1 n.c. delay-2 vref sec-cont remote delay-3 n.c. vcc out-a out-b out-c out-d out-e out-f n.c. n.c. n.c. n.c. pgnd sgnd rt ramp-slp n.c. n.c. n.c. n.c. n.c. sync n.c. 30 29 28 27 26 25 24 23 22 21 12345678910 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 delay-1 cs ramp ss rt delay-2 comp vref vcc ramp-slp gnd 12 11 fb(?) out-a out-b out-c out-d out-e out-f delay-3 10 sync 1 (top view) outline: lqfp-40 (plqp0040jb-c) n.c.: non-connection (top view) outline: sop-20 (prsp0020dd-b) r2a20124afp r2a20124asp
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 4 of 12 mar 11, 2011 pin functions lqfp-40 pin no. sop-20 pin no. pin name i nput/output pin function 1 8 delay-1 input/output delay time adjustor for the full-bridge control signal (out-a and b) 2 9 delay-2 input/output delay time adjustor for the full-bridge control signal (out-c and d) 4 10 delay-3 input/output delay time adjustor fo r the secondary control signal (out-e and f) 5 ? sec-cont input synchronous rectification on/off control 6 ? remote input remote on/off control 7 11 vref output 5 v/20 ma output 9 12 vcc input ic power supply input 13 13 out-f output secondary control signal 14 14 out-e output secondary control signal 17 15 out-d output full-bridge control signal 18 16 out-c output full-bridge control signal 19 17 out-b output full-bridge control signal 20 18 out-a output full-bridge control signal 22 ? pgnd ? ground level for the output signal 23 ? sgnd ? ground level for the small signal ? 19 gnd ? ground 24 20 rt input/output timing resistor for the oscillator 27 1 sync input/output synchronization i/o for the oscillator 29 2 ramp-slp input/output ramp sloping adjustor 31 3 ramp input ramp waveform set 33 4 cs input current sense signal input for ocp 34 ? cs-out output current s ense information amplifier output 36 5 comp output error amplifier output 37 6 fb(?) input error amplifier negative input 38 7 ss output timing capacitor for soft start 3, 8, 10 to 12, 15, 16, 21, 25, 26, 28, 30, 32, 35, 39, 40 ? n.c. ? open
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 5 of 12 mar 11, 2011 block diagram r2a20124afp uvlo h l vcc 4 v h l oscillator res q sgnd comparator vcc vref vref vref clamp circuit vcc vcc vcc vcc vcc pgnd 1.135 v vref good vref good vref good 1.25 v vref heavy load vref 40 a 500 a 10 a 10 a 2.5 k 185 k 1.15 v 1.4 v zero delay res res vref out-a delay-1 out-b out-c delay-2 out-d delay-3 out-e out-f rt remote sync comp ramp ramp-slp ss cs-out cs sec-cont on: 1.32 v off: 1.23 v start-up counter 32 clock 5 v generator fb(?) sync i/o error amp 3.0 pulse by pulse vref good circuit bias phase shift control logic delay control circuit delay control circuit synchronous rectification control logic
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 6 of 12 mar 11, 2011 r2a20124asp uvlo h l 4 v h l oscillator res q sync i/o comparator vcc vref 500 a 10 a vref vref clamp circuit gnd 1.135 v vref good vref good vref good 1.25 v vref 1.4 v vcc res res vcc vcc vcc vcc vcc zero delay rt sync comp ramp ramp-slp ss cs out-f out-e delay-3 out-d delay-2 out-c out-b delay-1 out-a vref fb(?) 5 v generator vref good circuit bias start-up counter 32 clock error amp pulse by pulse phase shift control logic delay control circuit delay control circuit synchronous rectification control logic
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 7 of 12 mar 11, 2011 absolute maximum ratings (ta = 25c) item symbol ratings unit note power supply voltage vcc 20 v 1 peak output current ipk-out ? 200 ma 2, 3 dc output current idc-out ? 50 ma 3, 4 vref output current iref-out ?20 ma 3 comp sink current isink-comp 2 ma 3 delay set current iset-delay 0.3 ma 3 rt set current iset-rt 0.3 ma 3 ramp-slp set current iset-ramp-slp 0.3 ma 3 vref terminal voltage vter-ref ?0.3 to +6 v 1, 5 terminal group 1 voltage vter-1 ?0.3 to (vref + 0.3) v 1, 6 operating junction temperatur e tj-opr ?40 to +125 c 7 storage temperature tstg ?55 to +150 c notes: 1. rated voltages are with reference to the gnd or sgnd pin. 2. the rating shows the transient current when driving a capacitive load. 3. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 4. total current of out-a, out-b, out-c, out-d, out-e, and out-f must be not exceed ? 90 ma. 5. vref pin voltage must not exceed vcc pin voltage. 6. terminal group 1 is defined the pins; remote, ramp-slp, sec-cont, cs , ramp, comp, cs-out, fb(?), ss, rt, sync, and delay-1 to 3 7. theramal resistance ? ja r2a20124afp (40-pin); 85.3c/w board condition; glass epoxy 50 mm ? 50 mm ? 1.6 mm, 10% wiring density. r2a20124asp (20-pin); 120c/w board condition; glass epoxy 40 mm ? 40 mm ? 1.6 mm, 10% wiring density.
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 8 of 12 mar 11, 2011 electrical characteristics (ta = 25c, vcc = 12 v, rt = 180 k ? , rdelay = 51 k ? , rramp-slp = 27 k ? , unless otherwise specified.) item symbol min typ ma x unit test conditions supply: r2a20124afp/asp start threshold vh 7.7 8.4 9.1 v shutdown threshold vl 7.4 8.0 8.6 v uvlo hysteresis dvuvl 0.3 0.4 0.5 v start-up current is ? 90 150 ? a vcc = 7.5 v operating current icc ? 8 11.5 ma no load on vref pin vref: r2a20124afp/asp output voltage vref 4.9 5.0 5.1 v line regulation vref-line ? 0 10 mv vcc= 10 v to 16 v load regulation vref-load ? 6 20 mv iref= ?1 ma to ?20 ma temperature stability dvref/dta ? ? 80 * 1 ? ppm/c ta = ?40c to 105c oscillator: r2a20124afp/asp oscillator frequency fosc ? 200 * 1 ? khz switching frequency fsw 85 100 115 khz measured on out-a, -b line stability fsw-line ?1.5 0 1.5 % vcc = 10 v to 16 v temperature stability dfsw/dta ? ? 0.1 * 1 ? %/c ta = ?40c to 105c rt voltage v rt 2.5 2.7 2.9 v sync: r2a20124afp/asp input threshold v th-sync 2.5 2.85 3.2 v output high v oh-sync 3.5 4.0 ? v rsync = 33 k ? to gnd * 2 output low v ol-sync ? 0.10 0.18 v rsync = 33 k ? to vref minimum input pulse t i-min 50 ? ? ns output pulse width t o-sync ? 3.0 * 1 ? ? s remote: r2a20124afp on threshold voltage v on-remote 1.12 1.32 1.52 v off threshold voltage v off-remote 1.04 1.23 1.42 v remote hysteresis dvremote 60 90 120 mv input bias current i remote ?100 ?50 ? ? a remote = 2 v error amplifier: r2a20124afp/asp fb(?) input voltage v fb(?) 1.225 1.250 1.275 v fb(?) and comp are shorted fb(?) input current i fb(?) ?2.0 0 2.0 ? a fb(?) = 1.25 v open-loop dc gain av ? 80 * 1 ? db unity gain bandwidth bw ? 2 * 1 ? mhz output source current i source ?650 ?500 ?390 ? a fb(?) = 0.75 v, comp = 2 v output sink current i sink 2.0 6.5 ? ma fb(?) = 1.75 v, comp = 2 v output high voltage v oh-eo 3.7 3.9 ? v fb(?) = 0.75 v, comp; open output low voltage v ol-eo ? 0.1 0.4 v fb(?) = 1.75 v, comp; open output clamp voltage * 3 v clamp-eo ?0.16 ?0.07 0.0 v fb(?) = 0.75 v, comp; open, ss = 1 v notes: 1. design specif ication (reference data) 2. r2a20124afp: sgnd and pgnd 3. v clamp-eo = v comp ? ss voltage (1 v)
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 9 of 12 mar 11, 2011 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, rt = 180 k ? , rdelay = 51 k ? , rramp-slp = 27 k ? , unless otherwise specified.) item symbol min typ ma x unit test conditions phase modulator: r2a20124afp/asp ramp offset voltage v ramp 1.035 1.135 1.235 v ramp source current isource- ramp ?220 ?185 ?150 ? a ramp = 0.15 v, comp; open ramp sink current i sink-ramp 3 10 ? ma ramp = 0.15 v, comp = 0 v minimum phase shift dmin ? 0 * 1 * 4 ? % ramp = 0 v, comp = 0 v maximum phase shift dmax ? 97.0 * 1 * 4 ? % ramp = 0 v, comp = 2.1 v delay to out-c, -d * 2 tpd ? 100 200 ns comp = 1.6 v ramp discharge time * 1 tdis ? 80 120 ns fb(?) = 0.75 v, comp; open ramp-slp voltage v ramp-slp 2.1 2.3 2.5 v delay: r2a20124afp/asp delay-1, -2 * 3 t d1, 2 70 100 130 ns delay set r = 51 k ? delay-3 * 3 t d3 45 65 85 ns delay set r = 51 k ? delay2-1, -2 * 1 * 3 t d2_1, _2 140 220 300 ns delay set r = 180 k ? delay2-3 * 1 * 3 t d2_3 110 170 230 ns delay set r = 180 k ? terminal voltage v d1, 2, 3 1.9 2.0 2.1 v delay set r = 51 k ? soft start: r2a20124afp/asp source current i ss ?14 ?10 ?6 ? a ss = 1 v ss high voltage v oh-ss 3.9 4.0 4.1 v notes: 1. design specif ication (reference data) 2. tpd is defined as; ramp out-c/d tpd 0 v 1 v 50% 50% vcc 0 v 3. t d1 , t d2 , and t d3 are defined as; out-a out-b out-c out-d out-e out-f t d1 t d1 t d2 t d2 t d3 t d3 50% for primary control for secondary control 4. maximum/minimum phase shift is defined as; t1 t1 t2 out-a out-d t2 out-b out-c d = 2 100 (%) t2 t1
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 10 of 12 mar 11, 2011 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, rt = 180 k ? , rdelay = 51 k ? , rramp-slp = 27 k ? , unless otherwise specified.) item symbol min typ ma x unit test conditions over current protection: r2a20124afp/asp pulse-by-pulse current limit threshold v cs-pp 1.26 1.4 1.54 v sec-cont = 0.3 v (afp) delay to out pins * 1 tpd-cs ? 100 200 ns cs = 0 v to 1.57 v, sec-cont = 0.3 v (afp) cs sink current i sink-cs 2 5 ? ma cs = 0.15 v, comp = 0 v output: r2a20124afp/asp high voltage v oh-out 11.5 11.9 ? v iout = ?2 ma low voltage v ol-out ? 0.05 0.2 v iout = 2 ma rise time tr ? 30 100 ns cout = 100 pf fall time tf ? 30 100 ns cout = 100 pf timing offset * 2 t d4 ? 20 140 ns power information amplifier: r2a20124afp tranceconductance gm 15 20 25 ? s cs = 0.4 v secondary control: r2a20124afp forced synchronous rectification on voltage von-sec-cont 4.6 ? ? v cs = 1 v forced synchronous rectification off voltage voff-sec-cont ? ? 0.4 v cs = 0 v input bias current-1 i sec-cont1 5 10 20 ? a cs = 0 v, sec-cont = 2.1 v input bias current-2 i sec-cont2 10 20 40 ? a cs = 1 v, sec-cont = 2.1 v current hysteresis di sec-cont 5 10 20 ? a notes: 1. tpd-cs is defined as; tpd-cs cs out-c/d 0 1.57 v 50% 50% 2. t d4 is defined as; out-d out-e t d4 50% 50% out-c out-f t d4 50% 50%
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 11 of 12 mar 11, 2011 timing diagram note: all voltage, current, time shown in the diagram is typical value. out-a out-b out-c out-d out-e out-f out-a out-b out-c out-d out-e out-f t d1 t d1 t d2 t d2 t d3 t d3 low-fixed low-fixed t d1 t d1 t d2 t d2 out-a out-b out-c out-d ramp out-f out-e ma mb mc md me mf drive drive drive drive drive drive vin external power stage ? full bridge and secondary control: r2a20124afp/asp ? full bridge and secondary control: r2a20124afp (sec-cont > 4.6 v)
r2a20124afp/r2a20124asp preliminary r03ds0031ej0300 rev.3.00 page 12 of 12 mar 11, 2011 package dimensions note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. index mark * 1 * 2 * 3 20 21 30 31 10 11 xm y p f 1 40 d e d e b z h e z h d 2 1 1 detail f c a l l a a terminal cross section ( ni/pd/au plating ) p c b 1.40 1.70 1.0 0 8 0.65 0.10 0.15 0.20 0.17 0.22 0.27 8.8 9.0 9.2 7.0 0.50 9.2 9.0 8.8 0.13 0.10 0.13 7.0 l 1 z e z d y x c b 1 b p a h d a 2 e d reference symbol dimension in millimeters min nom max a 1 c 1 e e l h e 0.08 0.22 0.575 0.575 0.40 0.60 p-lqfp40-7x7-0.65 0.2g mass[typ.] fp-40ev plqp0040jb-c renesas code jeita package code previous code 0.80 0.15 1.27 7.50 8.00 0.40 0.34 a 1 13.0 max nom min dimension in millimeters symbol reference 2.20 0.90 0.70 0.50 5.50 0.20 0.10 0.00 0.46 0.25 0.20 0.15 7.80 8 0 0.12 1.15 12.60 l 1 z h e y x c b p a 2 e d b 1 c 1 e e l a 20 11 10 f * 1 * 2 * 3 p m x y 1 e index mark d e h b z a terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. p-sop20-5.5x12.6-1.27 0.31g mass[typ.] fp-20dav prsp0020dd-b renesas code jeita package code previous code
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1

▲Up To Search▲

Price & Availability of R2A20124ASP-W0

	To Download R2A20124ASP-W0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .